[Fwd: Submission of the Verilog-AMS LRM v2.3/draft4a for Accellera Board approval]

Hi all,

I am forwarding the notification that I sent through to the Accellera 
Board submitting the Verilog-AMS v2.3/draft4a for approval. I realized 
just after I had sent out the email that the reflector would not accept 
the original email with the big attachment.

Regards,
Sri

-------- Original Message --------
Subject: Submission of the Verilog-AMS LRM v2.3/draft4a for Accellera 
Board approval
Date: Thu, 22 May 2008 10:58:54 +0530
From: Sri Chandra <sri.chandra@freescale.com>
Organization: Freescale Semiconductor Inc.
To: accellera_bod@accellera.org, Karen Pieper <karen_l_pieper@yahoo.com>
CC: Verilog-AMS LRM Committee <verilog-ams@eda.org>,  Sri Chandra 
<sri.chandra@freescale.com>


Dear Karen, Accellera Board Members,

The Verilog-AMS technical committee has completed the work and the
internal review process on the Verilog-AMS LRM version 2.3. On behalf of
the Verilog-AMS technical committee, it is my pleasure to submit LRM
v2.3/draft4a for the Accellera approval process.

This standard is an extremely important milestone for the technical
committee with an unified Verilog-AMS language integrating the previous
Verilog-AMS standard, LRM v2.2, with the IEEE 1364-2005 standard. We
have also included a host of analog and mixed signal features to enable
efficient top-down AMS design methodology and verification. This
standard also addresses the language conflicts with the P1800
SystemVerilog standard. This version sets us up very well do the P1800
standard integration with AMS which is the next major challenge for this
committee along with certain specific mixed signal enhancements that
have been identified as part of the current work.

I also want to take this opportunity to thank all the volunteers who
have contributed a lot both in terms of invaluable technical
contribution as well as time over the last 3 years. Its been lot of
early morning/late night calls depending on the timezone across the
world. I also would like to thank the technical editor, Stu Sutherland,
for editing the draft versions and in making the document a professional
standard and consistent with the other IEEE standards documents.

All open issues in the language standard are being documented as part of
the mantis database, and will be taken up in the upcoming revisions of
the standard. If you have any additional queries or need additional
information please let me know. I have also included important weblinks
regarding the committee activities.

Accellera technical committee web page: http://www.eda.org/verilog-ams/
Verilog-AMS reflector: verilog-ams@eda.org
Mantis database: http://www.eda-stds.org/mantis/main_page.php (Project:
Verilog-AMS)

Looking forward for the approval of this standard by the Accellera board.

Best Regards,
Sri (on behalf of the Verilog-AMS technical committee)
-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
T:+91-120-439 5000 p:x3824 f: x5199

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