RE: Verilog-AMS v2.3/draft4a

Hi,

Clause 3 starts,

"Verilog-AMS HDL supports integer, genvar, real, and parameter data
types as found in IEEE std 1364-2005 Verilog HDL. It includes the string
data type defined by IEEE std 1800-2005 SystemVerilog. It also modifies
the parameter data types and introduces array of real as an extension of
the real data type."

Comments:

1. 1364-2005's genvar is not a data type.
Neither are parameters.


2. Arrays of real already exist in 1364-2005.
Perhaps the intent was arrays of parameters.


3. 3.3 has the example, two lines before Table 3-3,
"r = {"H",""}; // yields "H\0". "" is converted to 8'b0l".

That should be 8'b0, not 8'b01.


4. The BNF non-terminal constant_concatenation is used for array
initialization, as in 
real_type and variable_type in Syntax 3-1, param_assignment in Syntax
3-2, net_assignment in Syntax 3-6, for example. 

That non-terminal is missing the apostrophe preceding the curly brackets
that 3.4 says is needed: "For parameters defined as arrays, the
initializer shall be a constant_param_arrayinit expression which is a
list of constant expressions containing only constant numbers and
previously defined parameters within '{ and } delimiters."

And the "constant_param_arrayinit" mentioned there does not appear
anywhere.


5. In 3.4.2, "The use of brackets, [ and ], indicate inclusion of the
end points in the valid range. The use of parenthesis, ( and ), indicate
exclusion of the end points from the valid range. It is possible to
include one end point and not the other using [ ) and ( ]."

"parenthesis" should be plural, "parentheses".
"indicate" should be "indicates", twice.

Regards,
Shalom
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