Hi all, Stu has made final edits to the draft4a version of Verilog-AMS v2.3 and its been uploaded to the web site: http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/VAMS_v2.3-Draft4a.pdf Stu has addressed all the issues that were recorded as part of the last Verilog-AMS call on 20th May and minuted in the report. Any further errata, changes and new enhancements will be recorded as part of the Mantis database and will be taken up for the next version of the AMS LRM standard. I plan to send out the notification to Karen Pieper (technical chair for Accellera) and the board members possibly tomorrow for the review of this standard by the board and the approval of this version. Regards, Sri -- Srikanth Chandrasekaran Design Technology (Tools Development) Freescale Semiconductor Inc. T:+91-120-439 5000 p:x3824 f: x5199 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed May 21 11:49:43 2008
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