RE: more Clause 3 comments

Even after a timepoint?

At least one simulator starts wires at x deliberately and then drives
them to z in order that there be a transition at time 0 in order to
trigger continuous assignments and always blocks, etc.

Shalom

> -----Original Message-----
> From: owner-verilog-ams@server.eda.org 
> [mailto:owner-verilog-ams@server.eda.org] On Behalf Of David Miller
> Sent: Wednesday, June 04, 2008 7:29 PM
> To: Nourdine Belhous
> Cc: Verilog-AMS LRM Committee
> Subject: Re: more Clause 3 comments
> 
> Hi Nourdine,
> Thanks, I changed my example to be 'wire mywire' instead.
> Unfortunately, when I tried this with two different 
> commercial digital simulators, one gives
>    mywire = x
> 
> the other
>    mywire = z
> 
> So even the pure digital simulators don't seem to agree.
> 
> Cheers...
> Dave
> 
> 
> Nourdine Belhous wrote:
> > Hi,
> > If you want to test the initial value of a net, you should 
> declare a 
> > wire (or anything specified as a net in the digital LRM) 
> instead of a 
> > register.
> > And you'll probably get a value of 'z' from the simulator.
> > 
> > Nourdine BELHOUS.
> > 
> > David Miller wrote:
> >>
> >>>
> >>> 3.7: "Unlike other digital nets which have an initial 
> value of 'x',..."
> >>> Digitial nets have an initial value of z, not x.
> >>>
> >>
> >> I am confused.
> >> If I have:
> >>
> >> module test;
> >> reg myreg;
> >> initial $display("myreg = %b",myreg); endmodule
> >>
> >> Digital simulators print:
> >>   myreg = x
> >>
> >> How is this value different from the initial value of myreg?
> >>
> >>
> >> Dave
> >>
> >>
> >>
> > 
> > 
> 
> --
> ==============================================
> -- its another day for you and me in paradise
> --
> -- David Miller
> -- Design Technology (Austin)
> -- Freescale Semiconductor
> -- Ph : 512 996-7377 Fax: x7755
> ==============================================
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