Hi, 6.2 says, "The definitions for module_item_declaration and parameter_override are shown in Syntax 6-2," but module_item_declaration does not exist anywhere. Also, the LRM contains a few examples of identifiers called "ref". It would be best to change them, as 'ref' is a keyword in SystemVerilog. Regards, Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6582 +972 54 721-1033 --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sun Jun 15 07:15:44 2008
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