Re: Clause 4

Bresticker, Shalom wrote:

> Table 4-2 lists concatenation and replication as legal with real 
> expressions. They are not legal in V2K5. Nor does this document 
> specify how they would behave with real expressions, in contrast to 
> modulus, which IS specified.
>
Hi

I've just been reading over 4.2.13, and though it does make some things 
clearer, I think that some necessary information has been lost as well.

The text and the examples look very similar to the Verilog 2005 standard.

For instance, the the LRM2.2, the first sentence is

A concatenation is used for joining scalar elements into compound 
elements (buses or
arrays) for the built-in types integer or real, or for elements declared 
of type
net_discipline.

In the 2.3LRM draft, there is no longer any mention of compound 
elements. Equally, in the case of compound elements, unsized numbers 
should be allowed.

I don't think that there is any problem with either concatenations or 
replication taking a real value. It just needs to be rounded to integer.

My view is that it is the type of the ltype should call the shots.

   1. scalar, integral ltype -> concatenation made up of sized integral
      numbers
   2. scalar, real ltype -> not allowed
   3. compound, integer ltype -> concatenation made up of unsized
      integers or reals (to be rounded to integer), not necessarily constant
   4. compound, real  ltype -> concatenation made up of unsized integers
      (converted to reals) or integers, not necessarily constant.
   5. string -> made up of strings

Regards
Paul Floyd
-- 
Dr Paul Floyd
Mentor Graphics Corporation


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