RE: Clause 4

Paul,

If I understand you, you are referring to use of concatenation for array
literals.

I had previously commented (on a previous draft) that in SV, such forms
require the brackets to be prefixed by an apostrophe and are not called
concatenations.

On Clause 3, I commented thus:

"The BNF non-terminal constant_concatenation is used for array
initialization, as in real_type and variable_type in Syntax 3-1,
param_assignment in Syntax 3-2, net_assignment in Syntax 3-6, for
example. 

That non-terminal is missing the apostrophe preceding the curly brackets
that 3.4 says is needed: "For parameters defined as arrays, the
initializer shall be a constant_param_arrayinit expression which is a
list of constant expressions containing only constant numbers and
previously defined parameters within '{ and } delimiters."

And the "constant_param_arrayinit" mentioned there does not appear
anywhere."


And 4.2.13 itself says,

"The concatenation shall be expressed using the brace characters { and
}, with commas separating the expressions within. It should not be
confused with the array literal syntax '{ } which is array of values.
Confusion can arise because { } is the array literal syntax in the C
language whereas it means something very different in the Verilog HDL
and Verilog-AMS HDL languages."

Regards,
Shalom


> -----Original Message-----
> From: owner-verilog-ams@server.eda.org 
> [mailto:owner-verilog-ams@server.eda.org] On Behalf Of Paul Floyd
> Sent: Monday, June 30, 2008 5:16 PM
> Cc: Verilog-AMS LRM Committee
> Subject: Re: Clause 4
> 
> Bresticker, Shalom wrote:
> 
> > Table 4-2 lists concatenation and replication as legal with real 
> > expressions. They are not legal in V2K5. Nor does this document 
> > specify how they would behave with real expressions, in contrast to 
> > modulus, which IS specified.
> >
> Hi
> 
> I've just been reading over 4.2.13, and though it does make 
> some things clearer, I think that some necessary information 
> has been lost as well.
> 
> The text and the examples look very similar to the Verilog 
> 2005 standard.
> 
> For instance, the the LRM2.2, the first sentence is
> 
> A concatenation is used for joining scalar elements into 
> compound elements (buses or
> arrays) for the built-in types integer or real, or for 
> elements declared of type net_discipline.
> 
> In the 2.3LRM draft, there is no longer any mention of 
> compound elements. Equally, in the case of compound elements, 
> unsized numbers should be allowed.
> 
> I don't think that there is any problem with either 
> concatenations or replication taking a real value. It just 
> needs to be rounded to integer.
> 
> My view is that it is the type of the ltype should call the shots.
> 
>    1. scalar, integral ltype -> concatenation made up of 
> sized integral
>       numbers
>    2. scalar, real ltype -> not allowed
>    3. compound, integer ltype -> concatenation made up of unsized
>       integers or reals (to be rounded to integer), not 
> necessarily constant
>    4. compound, real  ltype -> concatenation made up of 
> unsized integers
>       (converted to reals) or integers, not necessarily constant.
>    5. string -> made up of strings
> 
> Regards
> Paul Floyd
> --
> Dr Paul Floyd
> Mentor Graphics Corporation
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