Date: 10th July 2008, 7:00-9:00am Pacific time Attendees: Martin O'Leary, Cadence Marek Mierzwinski, Tiburon Geoffrey Coram, Analog Devices Dave Cronauer, Synospsys Sri Chandra, Freescale If i have missed any attendees please let me know. Note: All references to sections and page numbers in the following minutes are based on LRM2.3/draft4 and page numbers refer to the ones on the top in the PDF. (<x>/401) General: ======== * The meeting focussed on the items submitted during the Accellera board review process between 22nd May and 24th June * Requested from Accellera regarding information on Board meeting and any further feedback but in parallel look at comments that have been submitted during that period * Its still unclear with regards to the availability of the editor. In discussions with the Accellera board on this. Title page: =========== * [pg 2/401]: "Suggestion for improvements to the Verilog hardware description language ..."; Verilog to be changed to Verilog-AMS Chapter 1: Verilog-AMS introduction =================================== * [Clause 1.2, pg 15]: In bullet point #4 the reference to "analog" is in the wrong font. Chapter 2: Lexical conventions ============================== * [Clause 2.4, pg 24]: End of first paragraph "on-line comment" should be changed to "one-line comment". * [Clause 2.6.1, pg 26]: Change the following sentence "See 8.1.6 of IEEE std 1364-2005 Verilog HDL and Table 8-1 of IEEE std 1364-2005 Verilog HDL" to "See Table 8-1 in 8.1.6 of IEEE std 1364-2005 Verilog HDL" * [Clause 2.7, pg 29]: Change section heading from "Strings" to "String literals". This has been done in P1800 with the addition of the string data type. * [Clause 2.8.3, Syntax 2-3, pg 32]: The digital version of system task enable allows arguments to be optional even if parantheses and comma are specified. Same to be done for AMS. This change should be done in Annex A.6.9 also. Change: analog_system_task_enable ::= analog_system_task_identifier [ ( analog_expression { , analog_expression } ) ] ; to analog_system_task_enable ::= analog_system_task_identifier [ ( [ analog_expression ] { , [ analog_expression ] } ) ] ; * [Clause 2.8.3, Syntax 2-3, pg 32]: The digital version of system task function allows arguments to be optional even if parantheses and comma are specified. Same to be done for AMS. Same to be done for Annex A.8.2 Change: analog_system_function_call ::= analog_system_function_identifier [ ( analog_expression { , analog_expression } ) ] to analog_system_function_call ::= analog_system_function_identifier [ ( [ analog_expression ] { , [ analog_expression ] } ) ] * [Clause 2.8.3, pg 32]: The references to Clause 8, 10, and 12 of 1364-2005 may be incorrect. This was discussed in the committee and its unclear at this point whether some of the clauses are internal references to Verilog-AMS document itself. Also chapter numbers have changed in p1364 and LRM2.3 and need to do detailed search for any reference to system task/function on these before removing these clauses. ==> *Note:* This is not planned for this version and will be taken for next revision and also deemed as not very critical. * [Clause 2.8.4, pg 32]: The reference to Clause 11 of 1364 might be incorrect. This was discussed in the committee and its unclear at this point whether some of the clauses are internal references to Verilog-AMS document itself. Also chapter numbers have changed in p1364 and LRM2.3 and need to do detailed search for any reference to system task/function on these before removing these clauses. ==> *Note:* This is not planned for this version and will be taken for next revision and also deemed as not very critical. Chapter 3: Data types ===================== * [Clause 3.1, pg 37]: genvar and parameters are not data types in digital LRM. It was checked that p1364 refers to parameter as data types (4.10?). Its clarified that this is being taken up in P1800-2009 and this issue is dropped. * [Clause 3.2, pg 37]: "Arrays of real" exists in P1364 already. This should be changed to "Arrays of parameter" * [Clause 3.3, pg 39]: In the example code; r = {"H",""}; the comment should be changed from 8'b01 to 8'b0 * [Clause 3.1, syntax 3-1, pg 37]: [Clause 3.4, syntax 3-2, pg 40/41]: constant_concatenation BNF is being used for param_assignment. constant_concatenation does not have the leading apostrophe. The constant_arrayinit (instead of constant_param_arrayinit) should be used in this syntax which will have the apostrophe (and constant_arrayinit should also be defined in BNF A.8.1 also which is missing). This mistake was due to the fact that in early draft versions array literals and concatenations were not distinguished in the AMS LRM. This change needs to be done in A.2.4 also. parameter_identifier = constant_mintypmax_expression { value_range } | parameter_identifier_range = constant_arrayinit { value_range } * [Clause 3.4.2, pg 42]: In paragraph 2, "The use of brackets, ..." change this to "Brackets, [ and ], indicate inclusion of end points in the valid range". Also change next sentence to "Parantheses, ( and ), indicate exclusion ..." (note: plural for parantheses). * [Clause 3.6, pg 46]: Para 2, "all continuous nets segments" to be changed to "all continuous net segments" * [Clause 3.6.1.2, pg 48]: In abstol description, the current text it missing a word. The sentence "It specifies the maximum negligible for signals ..." should read "It specifies the maximum negligible value for signals ..." * [Clause 3.6.3, pg 53]: "A vector net is also called an bus" should read "A vector net is also called a bus" * [Clause 3.6.3.2, pg 54]; In example null argument is allowed. electrical [0:4] bus = '{2.3,4.5,,6.0}; This requires new syntax item and Syntax 3-6 and A.2.4 needs to be updated. net_assignment::= net_identifier [ = constant_expression] |net_identifier {dimension} [ = constant_optional_arrayinit ] |hierarchical_net_identifier and need to add constant_optional_arrayinit to be added to syntax/BNF (A.8.1) * [Clause 3.6.5, pg 55]: Delete "a" in first paragraph. "Nets can be used in structural descriptions without being declared". * [Clause 3.7, pg 55]: In paragraph 1, initial value of 'x' to be changed to initial value of 'z'. * [Clause 3.9, pg 56]: In paragraph 2, reference to E.4.3 should be changed to E.4.2.2 * [Clause 3.13.3, pg 60]: In para 1, change reference to "module block" to "module scope". * [Clause 3.13.4, pg 61]: In para 1, change reference to "module block" to "module scope". * [Clause 3.13.4, pg 61]: In last para, change "can be used to reference a net" to "can be used to reference a branch". Chapter 4: Expressions ====================== * [Clause 4.2.1, pg 63]; Table 4-2 lists concatenation and replication as legal with real expressions. They are not legal in 1364-2005. The intent here was to refer to array literal. The last row in this table to be deleted. * [Clause 4.2.2, pg 64]: Add ',(event)' operator to the precedence table along with || and or in Table 4-3. * [Clause 4.2.9, pg 68]; Table 4-12 should be inverse of table 4-11. The two rows should have values of 1 0 (first row) and 0 1 (second row). * [Clause 4.2.9, pg 68]: The last paragraph does not apply to signed operands. This was rectified as part of P1800-2009 and the following text from that LRM would be used: When one or both operands are unsigned, the expression shall be interpreted as a comparison between unsigned values. If the operands are of unequal bit lengths, the smaller operand shall be zero-extended to the size of the larger operand. When both operands are signed, the expression shall be interpreted as a comparison between signed values. If the operands are of unequal bit lengths, the smaller operand shall be sign-extended to the size of the larger operand. * [Clause 4.2.11, pg 69]: In the second example, the text below the example should say "shifted to the right one position" instead of "two positions". * [Clause 4.3, pg 71]: The last sentence in para 1, "follow tables" to be changed to "following tables" Chapter 5: Analog behavior ========================== * [Clause 5.10, pg 122]: In syntax 5-13 add "," also for analog_event_expression. This needs to be added to A.6.5 also. analog_event_expression ::= ... | analog_event_expression or analog_event_expression | analog_event_expression , analog_event_expression ("," in bold red) * [Clause 5.10, pg 122]: In syntax 5-13, the last semicolon at the very end should be bold red. -> | { attribute_instance } ; Chapter 6: Hierarchical structures ================================== * [Clause 6.2, pg 130/131]: Merge syntax 6-1 and 6-2 and remove the sentence between them ("The definitions for ...") * [Clause 6.2.2, pg 133]: change "ref" to "aref" in example (global search) as "ref" is a keyword in systemverilog. * [Clause 6.5.1, pg 143]: Changed the title to "Port definition" from "Port association". * [Clause 6.5.1, pg 143]: Add 4th bullet point - "A vector net formed as a result of the concatenation operator". * [Clause 6.5.1, pg 143]: Remove the restriction in last paragraph (first sentence of the last paragraph). Appendix A: BNF =============== * [Clause A.2.2.1, pg 342]: change constant_concatenation to constant_arrayinit in the following BNF real_type ::= real_identifier { dimension } [ = constant_concatenation ] variable_type ::= variable_identifier { dimension } [ = constant_concatenation ] to real_type ::= real_identifier { dimension } [ = constant_arrayinit ] variable_type ::= variable_identifier { dimension } [ = constant_arrayinit ] * [Clause A.2.4, pg 343]: Change constant_concatentation to constant_optional_arrayinit in the following BNF net_assignment ::= net_identifier [ = constant_expression ] | net_identifier { dimension } [ = constant_concatenation ] | hierarchical_net_identifier to net_assignment ::= net_identifier [ = constant_expression ] | net_identifier { dimension } [ = constant_optional_arrayinit ] | hierarchical_net_identifier * [Clause A.2.4, pg 343]: Change the constant_concatenation to constant_arrayinit in the following BNF param_assignment ::= parameter_identifier = constant_mintypmax_expression { value_range } | parameter_identifier range = constant_concatenation { value_range } to param_assignment ::= parameter_identifier = constant_mintypmax_expression { value_range } | parameter_identifier range = constant_arrayinit { value_range } * [Clause A.6.5, pg 352]: Add the BNF which uses "," operator to the BNF for analog_event_expression as the last item. analog_event_expression ::= ... | analog_event_expression or analog_event_expression | analog_event_expression , analog_event_expression ("," in bold red) * [Clause A.6.9, pg 339]: Make arguments to the analog_system_task_enable optional even when parantheses are specified (same as digital) analog_system_task_enable ::= analog_system_task_identifier [ ( analog_expression { , analog_expression } ) ] ; to analog_system_task_enable ::= analog_system_task_identifier [ ( [ analog_expression ] { , [ analog_expression ] } ) ] ; * [Clause A.8.1, pg 358]: Add the following new BNF grammer "constant_arrayinit" and "constant_optional_arrayinit" after the constant_concatenation BNF item. The items should be in blue as they are analog. constant_arrayinit ::= '{ constant_expression { , constant_expression } } constant_optional_arrayinit ::= '{ [ constant_expression ] { , [ constant_expression ] } (first/last curly {} in bold red) * [Clause A.8.2, pg 358]: Make the arguments optional for analog_system_function call even if parantheses are specified. analog_system_function_call ::= analog_system_function_identifier [ ( analog_expression { , analog_expression } ) ] to analog_system_function_call ::= analog_system_function_identifier [ ( [ analog_expression ] { , [ analog_expression ] } ) ] Additional comments =================== *Note 1:* Addition of 2 new BNF items constant_arrayinit (for array parameters and variables) and constant_optional_arrayinit for analog net declarations (where some of the arguments can be optional) on A.8.1. This has impact on A.2.2.1 and A.2.4 which refer to constant_concatenation. The rest of the BNF corrections specified are minor. *Note 2:* Two of the suggestions namely wrong cross-references in clauses 2.8.3 and 2.8.4 are not planned for this revision. If i have missed anything please feel free to add. Regards, Sri -- Srikanth Chandrasekaran Design Technology (Tools Development) Freescale Semiconductor Inc. T:+91-120-439 5000 p:x3824 f: x5199 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Jul 11 01:33:27 2008
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