Re: Minutes of the Verilog-AMS meeting: 10th July 2008

Shalom,

Thanks for your response and clarifying the text on that.

We had a bit of discussion on this item and we were not clear what the 
references are intended for, and what the correct references should be 
for both the system tasks and functions. It was acknowledged during the 
meeting that the references may be in error (due to chapter 
addition/deletions) or sections having been moved. However, it was felt 
in the discussions that it was probably a minor issue which might take 
more time to actually figure out the correct ones and leave them there. 
May be not the best approach but since during the discussions it was 
felt as a minor item.

I understand your concern, and greatly appreciate the feedback that we 
would like to incorporate in the LRM, and apologize that you find this 
particular decision ridiculous. I will take another look at this 
particular issue that you have mentioned.

Regards,
Sri



Bresticker, Shalom wrote:
> Hi,
> 
> Regarding the cross-references to IEEE Std 1364-2005 claues for system
> tasks and functions and compiler directives, the internal references
> appear immediately following the texts in question:
> 
> The $identifier system task or function can be defined in five places
> - A standard set of $identifier system tasks and functions, as defined
> in Clause 8, Clause 10, Clause 17 and Clause 18 of IEEE std 1364-2005
> Verilog HDL.
> - Additional $identifier system tasks and functions defined using the
> PLI, as described in Clause 12 and Clause 20 of IEEE std 1364-2005
> Verilog HDL.
> - Additional $identifier system tasks and functions defined in Clause 4
> and Clause 9 of this standard.
> - Additional $identifier system tasks and functions defined using the
> VPI as described in Clause 11 and Clause 12 of this standard.
> - Additional $identifier system tasks and functions defined by software
> implementations. 
> 
> and
> 
> The `identifier compiler directive construct can be defined in three
> places
> - A standard set of `identifier compiler directives defined in Clause 11
> and Clause 19 of IEEE std 1364-2005 Verilog HDL.
> - Additional `identifier compiler directives defined in Clause 10 of
> this standard.
> - Additional `identifier compiler directives defined by software
> implementations.
> 
> Thus the references to Clauses 8, 10, 11, and 12 are clearly wrong and
> it is ridiculous to leave them. The correct references do appear and
> therefore these should be simply deleted. Even if you can claim that
> maybe they were intended to refer to something else and you want to find
> out what that was, it makes no sense to leave them in their current
> form. Delete them now, and if you find in the future an additional
> reference that should have appeared, add it then. As they are now, they
> do not help anyone, and just confuse.
>  
> 
>> * [Clause 2.8.3, pg 32]: The references to Clause 8, 10, and 12 of 
>> 1364-2005 may be incorrect. This was discussed in the 
>> committee and its 
>> unclear at this point whether some of the clauses are internal 
>> references to Verilog-AMS document itself. Also chapter numbers have 
>> changed in p1364 and LRM2.3 and need to do detailed search for any 
>> reference to system task/function on these before removing 
>> these clauses.
>> ==> *Note:* This is not planned for this version and will be 
>> taken for 
>> next revision and also deemed as not very critical.
>>
>> * [Clause 2.8.4, pg 32]: The reference to Clause 11 of 1364 might be 
>> incorrect. This was discussed in the committee and its 
>> unclear at this 
>> point whether some of the clauses are internal references to 
>> Verilog-AMS 
>> document itself. Also chapter numbers have changed in p1364 
>> and LRM2.3 
>> and need to do detailed search for any reference to system 
>> task/function 
>> on these before removing these clauses.
>> ==> *Note:* This is not planned for this version and will be 
>> taken for 
>> next revision and also deemed as not very critical.
> 
> Regards,
> Shalom
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-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
T:+91-120-439 5000 p:x3824 f: x5199

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