Re: Draft 6 posted

There are still a couple misuses of concatenation:

4.5.1 Page 61 (76 of 402):
  - analog_constant_concatenation

4.6.4.3 Page 82 (97 of 402):
   The vector can either be a constant concatenation or an array parameter.

4.7.2.2 Page 85 (100 of 402):
4.7.2.3 Page 86 (101 of 402):
   If the inout argument is defined as an array ...
   or a concatenation of analog variables.

4.7.3 Page 87 (102 of 402):
   and a concatenation of two scalar analog variables has been used
   for the second argument.

9.20.6 Page 230 (245 of 402):
   Arrays may also be specified directly via the concatenation operator.


-Geoffrey


David Miller wrote:
> Hi all,
> 
> I have posted draft 6 to the web page.
> 
> For a version containing changebars (these are changes as a result of 
> todays conference call)
> http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/VAMS_v2.3-Draft6_with_changebars.pdf 
> 
> 
> 
> And for a clean, non-changebar version:
> http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/VAMS_v2.3-Draft6.pdf 
> 
> 
> 
> Cheers...
> Dave
> 

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