Re: Verilog-AMS committee meeting

Due to IP policy issues as yet unresolved between QCOM and Accellera, I cannot participate any longer.. 
_I_ have no idea what Accellera's IP policy is, but given Qualcomm's IP heavy business model, It is apparently too broad for our lawyers. 
jbd


 Jonathan David
j.david@ieee.org
jb_david@yahoo.com
http://ieee-jbdavid.blogspot.com
Mobile 408 390 2425



----- Original Message ----
From: Sri Chandra <sri.chandra@freescale.com>
To: Verilog-AMS LRM Committee <verilog-ams@eda.org>
Sent: Tuesday, September 2, 2008 1:01:06 AM
Subject: Verilog-AMS committee meeting


Hi all,

We should start thinking about the next phase of activities and have an 
initial discussion on the activities and task, probably on Sept 17th 
(Wednesday), at the regular 7am pacific time slot. (Is it okay to move 
the meeting a day earlier than our regular meeting day of Thursday?)

Call-In Details:
USA Toll Free: 877-346-8823
USA Toll: +1-203-320-0407
Passcode: 602538

Call times:
07:00am US Pacific
09:00am US Central
10:00am US Eastern
16:00pm Eindhoven
19:30pm Noida
23:30pm Adelaide


I am proposing the following agenda for the next meeting:
* Next tasks and activities
* Integration with P1800 std and discussion on moving to IEEE and status
* Other subcommittee activities that have started (assertions, AMS 
extensions)
* Initial understanding of timelines for the various activities and release
* Any other?

On the main P1800, We can identify and start work on the some of the 
smaller activities, starting with open issues that we couldn't close in 
the previous version.

Please feel free to add to the agenda.

Regards,
Sri
-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
T:+91-120-439 5000 p:x3824 f: x5199

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