RE: UPF/CPF - Handling power connections

Thanks for the update.

Unfortunately, at least in the case of SV, the language committee
members have neither the time nor the expertise to handle this.
Certainly there should be some coordination, though, to avoid the mess
that occurred this time around with the SV assertion enhancements. The
final product looks very good, but a lot of it had to be reworked,
delaying the new revision by many months.

Shalom

> -----Original Message-----
> From: owner-verilog-ams@server.eda.org 
> [mailto:owner-verilog-ams@server.eda.org] On Behalf Of Kevin Cameron
> Sent: Monday, August 04, 2008 8:45 PM
> To: verilog-ams
> Subject: UPF/CPF - Handling power connections
> 
> 
> Just a heads-up that stuff is going on at the p1801 committee 
> that you might want to be aware of:
> 
>     http://www.eda-stds.org/p1801/hm/0383.html - Proposal for 
> annotating attributes in Verilog, SystemVerilog, and VHDL
> 
>     http://www.eda.org/twiki/bin/view.cgi/P1801/WebHome
> 
> Strikes me that this is another case of unnecessary EDA 
> committee divergence. A chunk of the p1801 work should be 
> getting handled directly by SV/AMS/VHDL language committees - 
> e.g. attributes about power could be added into the AMS 
> discipline mechanism, and would be useful to proper 
> connect-module insertion.
> 
> Kev.
> 
> --
> True Circuits Inc. - http://www.truecircuits.com
> Tel: (650) 949 3400 Ext 3415
> 
> 
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