Minutes of Verilog-AMS committee meeting: 23 Oct 2008

Date: 23 Oct 2008, 7am Pacific
Attendees:
* Chris Vigil, IEEE
* Goeffrey Coram, Analog Devices
* Himyanshu Anand, Freescale
* Patrick O'Halloran, Tiburon
* Scott Little, Freescale,
* Ken Bakalar, Mentor Graphics
* Marq Kole, NXP
* Dave Cronauer, Synopsys
* Dave Miller, Freescale
* Sri Chandra, Freescale

Minutes:
* Chris gave a presentation on IEEE process and standards
   - detailed the process of moving from PAR to standard
   - Role and voting rights of the working group
   - Balloting rules
   - Detailed individual standard vs corporate standards
   - Fees required for voting on the working group and balloting for the 
different standards
For people who did not attend the meeting you can go through the 
presentation at
http://www.eda.org/verilog-ams/htmlpages/public-docs/IEEE_Standards_Development_Overview_10_23_08.ppt 


* Concerns, Queries
   - There was a query on why IEEE was accepting working group documents 
that have not been developed in adherence to IEEE standards and could be 
absorbed into IEEE (Mentor)
   - Queries and concerns regarding the services provided by IEEE as 
part of working within the IEEE organization, branding and financial 
services (Mentor)
   - Concern that corporate prorgram includes additional fees of $3900 
per project on yearly basis (no tax :)) for contributing and voting on 
the working group even for entities who are corporate members of IEEE. 
(Analog Devices, FSL). Need to get additional feedback from the 
committee regarding the participation within these standards
   - Individual membership has much lesser fee, however corporate 
program has one vote per entity and P1800 is already a corporate 
standard within IEEE (and Verilog-AMS is going to be a dot standard of 
P1800)

* Call time during US Winter
   - Last year the calls were at 9p Pacific time which is midnight in 
east coast and extremely early in the morning in Europe. Need to check 
participation from Australia etc and see whether the time zones can be 
made more friendly.
   - Plan to resolve timezone issue through email

* Could not cover open Mantis items as per the agenda. This will be 
taken up in the next call in November.

Next call: TBD (2nd or 3rd week of November)

Regards,
Sri
-- 
Srikanth Chandrasekaran
Design Technology (Tools Development)
Freescale Semiconductor Inc.
T:+91-120-439 5000 p:x3824 f: x5199

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.