Re: Next Verilog-AMS committee meeting: 13 Nov

You probably need to cc the SV-EC reflector to make sure everyone is 
aware. Might be a good idea to start a new reflector (say) "sv-ams" for 
this and the analog assertions discussions.

Kev.

Chandrasekaran Srikanth-A12788 wrote:
> Kevin,
>  
> I am not sure why you thought that my email implies that Verilog-AMS 
> would not be a part of SV effort. The presentation made by Chris Vigil 
> from IEEE detailed two options for the standards within IEEE - 
> individual standards effort and corporate standard.
>  
> I said in my email "also would like to hear which direction would you 
> or your corporation prefer going forward within the IEEE ..." meaning 
> which of the two options is preferable for you (individual vs 
> corporate) when we go with P1800 dot standard.
>  
> Sorry if this did not come out clearly. The intent is to make 
> Verilog-AMS as part of the SV (P1800) efforts and do it within IEEE.
>  
> Also, Geoffrey has put the document in the Verilog-AMS website and 
> also sent out the details of it to the reflector before the meeting 
> last week. I dont have the link with me right now, but if you cant 
> find his email or the document please let me know and I will try to 
> resend the link.
>  
> Regards,
> Sri
>
> ------------------------------------------------------------------------
> *From:* owner-verilog-ams@eda.org on behalf of Kevin Cameron
> *Sent:* Fri 10/24/2008 11:43 PM
> *To:* Verilog-AMS LRM Committee
> *Subject:* Re: Next Verilog-AMS committee meeting: 13 Nov
>
> Can you post a summary of the presentation and options going forward? -
> Your e-mail implies that Verilog-AMS wouldn't be part of the
> SystemVerilog effort.
>
> Kev.
>
> Sri Chandra wrote:
> >
> > Hi all,
> >
> > I am away for the next two weeks. Let us meet on 13th of November. I
> > would like to get feedback/concerns from you on the presentation that
> > was done yesterday by Chris Vigil from IEEE and also would like to
> > hear which direction would you or your corporation prefer going
> > forward within the IEEE so that we would be able to make a decision on
> > which option we chose for Verilog-AMS within the IEEE framework. We
> > would discuss this as the first agenda point when we meet. We also
> > need to start working on the PAR that needs to be submitted (within 6
> > months) as the study group was approved by the DASC.
> >
> > Regarding the time for conference calls, we had the following last
> > winter:
> >
> > 09:00 PM Pacific   (Thursday)
> > 11:00 PM Central   (Thursday)
> > Midnight Eastern
> > 06:00 AM Eindhoven (Friday)
> > 10:30 AM India     (Friday)
> > 03:30 PM Adelaide  (Friday)
> >
> > Graham - Could you let us know whether you will still be actively
> > participating in the calls since I have not heard from you for a
> > while. This will help us in understanding whether we can change the
> > timings so that US-central and east do not have to do midnight calls.
> > If not, we can stick to similar times for the winter also, any time
> > between 6am to 8.30am on the west coast which will be between 7.30pm
> > and 10pm in India (and 12.30pm-3am in Adelaide).
> >
> > Regards,
> > Sri
>
>
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