Analog Property Renderings

Hi,
    Freescale has posted some example renderings of AMS properties in an 
SVA-like syntax in the AMS Assertions folder on verilog-ams webpage. The 
link is given below.

http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/AMS_Assertions/fslASVApropertyRenderings_1.0.pdf 


    We would like to have a discussion on the property renderings in the 
next committee meeting. I will send out a reminder email tomorrow with 
agenda and call in details.

    The next meeting is on Nov 4th, 2008 from 11:30 am - 1:00 pm Central 
Standard Time (Winter Time, Note that US changes the time on Nov 2nd and 
the clocks will be set back one hour at 2:00 am on Nov 2nd, 2008)

Thanks,

-- 
Himyanshu Anand
EDA Strategy, Vendor Relation and Customer Collaboration,
Design Technology Organization,
Freescale Semiconductor

7700 W. Parmer Lane, Loc/MD: TX32/PL34
Austin, TX 78729
email  : Himyanshu.Anand@freescale.com
Ph     : +1-512-996-5623
Fax    : +1-512-996-7432



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