Updated: Analog System Verilog Assertions:

From: Anand Himyanshu <HIMYANSHU.ANAND_at_.....>
Date: Thu Oct 30 2008 - 11:46:59 PDT
When: Tuesday, November 04, 2008 11:30 AM-1:00 PM (GMT-06:00) Central Time (US & Canada).
Where: Dial In Access Code: 1848720

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Time: 11:30 AM - 1:00 PM Central Winter Time (Austin Time) (GMT - 6:00)

PS: Note the US changes time on Nov 2nd and the clocks will be reset one hour back.

Agenda:
  Discuss changes in meeting time (if required)
  Discuss example renderings of the analog properties in an SVA-like syntax. The document can be accessed at http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/AMS_Assertions/fslASVApropertyRenderings_1.0.pdf


- The current site for verilog-ams is http://eda.org/verilog-ams/ 
- Till a permanent home is found, documents released to the committee can be found at  http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/AMS_Assertions/

Dial In Access Code: 1848720
USA: +1-800-867-1147

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Received on Thu Oct 30 11:48:52 2008

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