Updated: Analog System Verilog Assertions

From: Anand Himyanshu <HIMYANSHU.ANAND_at_.....>
Date: Fri Nov 21 2008 - 09:40:43 PST
When: Occurs every Tuesday effective 12/2/2008 from 10:00 AM to 11:30 AM (GMT-06:00) Central Time (US & Canada).
Where: Time: 10:00 AM - 11:30 PM Central Standard Time (Austin Time) (GMT - 6:00)

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Time: 10:00 AM - 11:30 PM Central Standard Time (Austin Time) (GMT - 6:00)

Changing the time of the meeting due to winter time change in US.

- Twiki for Analog Assertions committee work: http://www.eda.org/twiki/bin/view.cgi/VerilogAMS/AmsAssertions
- The current site for verilog-ams is http://eda.org/verilog-ams/ 
- Some documents released to the committee can be found at  http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/AMS_Assertions/

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Received on Fri Nov 21 09:41:30 2008

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