Updated: Analog System Verilog Assertions

From: Anand Himyanshu <HIMYANSHU.ANAND_at_.....>
Date: Wed Nov 26 2008 - 12:58:09 PST
When: Tuesday, December 02, 2008 10:00 AM-11:30 AM (GMT-06:00) Central Time (US & Canada).
Where: Time: 10:00 AM - 11:30 PM Central Standard Time (Austin Time) (GMT - 6:00)

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Time: 10:00 AM - 11:30 PM Central Standard Time (Austin Time) (GMT - 6:00)

Changing the time of the meeting due to winter time change in US.

Agenda:

1) Discussion on interaction between digital engine and analog engine. 

There are some in the committee who have more digital exposure than analog and vice versa. It will help the committee as a whole if there is more discussion on the interaction between the digital and the analog engine.

Please feel free to add to the agenda.

- Twiki for Analog Assertions committee work: http://www.eda.org/twiki/bin/view.cgi/VerilogAMS/AmsAssertions
- The current site for verilog-ams is http://eda.org/verilog-ams/ 
- Some documents released to the committee can be found at  http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/AMS_Assertions/

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Received on Wed Nov 26 13:06:15 2008

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