Updated: Analog System Verilog Assertions

From: Anand Himyanshu <HIMYANSHU.ANAND_at_.....>
Date: Mon Jan 12 2009 - 13:26:43 PST
When: Tuesday, January 13, 2009 10:00 AM-11:30 AM (GMT-06:00) Central Time (US & Canada).
Where: Time: 10:00 AM - 11:30 AM Central Standard Time (Austin Time) (GMT - 6:00)

*~*~*~*~*~*~*~*~*~*

Time: 10:00 AM - 11:30 AM Central Standard Time (Austin Time) (GMT - 6:00)

This is a bi-weekly meeting.

Agenda:

1) Continuation of last meeting: Requirements for analog assertions and their interaction with the digital/analog engines, keeping in mind the future integration of System Verilog with Verilog-AMS language. 

2) Call for active participants to outline/collect requirements for analog assertions.


- Twiki for Analog Assertions committee work: http://www.eda.org/twiki/bin/view.cgi/VerilogAMS/AmsAssertions
- The current site for verilog-ams is http://eda.org/verilog-ams/ 
- Some documents released to the committee can be found at  http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/AMS_Assertions/

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