Updated: Analog System Verilog Assertions

From: Anand Himyanshu-R61978 <HIMYANSHU.ANAND_at_.....>
Date: Mon Apr 27 2009 - 08:23:12 PDT
When: Tuesday, April 28, 2009 10:00 AM-11:30 AM (GMT-06:00) Central Time (US & Canada).
Where: Time: 10:00 AM - 11:30 AM Central Standard Time (Austin Time) (GMT - 6:00)

*~*~*~*~*~*~*~*~*~*

Time: 10:00 AM - 11:30 AM Central Daylight/Summer Time (Austin Time) (GMT - 5:00)

Agenda:
1) Update on requirements gathering.
2) Discussion on possible extensions to bind statement to hook System Verilog Assertions extensions with Verilog AMS.

- Twiki for Requirements Gathering Group: http://www.eda.org/twiki/bin/view.cgi/VerilogAMS/RequirementsGatheringGroup
- Twiki for Analog Assertions committee work: http://www.eda.org/twiki/bin/view.cgi/VerilogAMS/AmsAssertions
- The current site for verilog-ams is http://eda.org/verilog-ams/ 
- Some documents released to the committee can be found at  http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/AMS_Assertions/

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