Expressions as part of port connections in module instantiations

My apologies if you receive this twice, I sent last week, but it never came 
through for me:

Jonathan David wrote:
 > So this type of connection would only be allowed to verification instances - 
not design instances (modules)?
 > jonathan

Well, not sure we should do that. I don't think we should introduce exceptions 
into the language depending on the type of instance that is being instantiated.

This problem is not directly a result of any SVA work. It is an issue with the 
existing LRM and the use of expressions connected to wreal.

I think maybe we need to take a look at chapter 7 - especially 7.3 for the next 
revision. It might need some more work.

For example, 7.3.6.4 states that only analog variables that are assigned within 
analog event statements can be used in continuous assignments, meaning:
   assign win = V(a);

is disallowed as per the language. If we are disallowing that, then it is 
contradictory to then allow:

   child ch1(V(a));

where port of child is a wreal. We can't really have one and not the other.

Cheers...
Dave



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