[Fwd: RE: Expressions as part of port connections in module instantiations]

Forwarded comments from Bob Floyd - silvaco

-------- Original Message --------
Subject: RE: Expressions as part of port connections in module instantiations
Date: Mon, 11 May 2009 09:12:15 -0700
From: Bob Floyd <bob.floyd@silvaco.com>
To: David Miller <David.L.Miller@freescale.com>

David,

Sorry, I don't participate often enough to have the proper instructions on
how to post. Feel free to
post it on my behalf if you wish.  Here are my comments.

>     child ch1(V(a))
>
> - and I would say that the latter is a signal-flow connection of the
> voltage of node 'a' (a PWL real value), as such it does not require an
> A2D. Any digital process sensitive to the port in ch1 (assign/@) gets an
> event at acceptance if V(a) changes.
>

"if V(a) changes" and "does not require an A2D" is an oxymoron:

For a variety of reasons, the numeric values in the solution vector at
adjacent timepoints is almost always different.

Without an A2D to threshold analog data, it can only be said "V(a) changes".
No "if" about it.  The A2D thresholding allows the "if".


Therefore, with regard to frequency of evaluation,

      child ck1(V(a))

is equivalent to

      child ck1(a)

Or, looking at child:

      module child(in);
        input in;
        always @in begin
           do something with in
        end

is no different than

      module child(in);
         input in;

         analog begin
           do something with in
         end

Because "always @in" will trigger at every time-point just as the analog
form does.

So why complicate the language to support "child ch1(V(a))" ?

Bob Floyd


>



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