List of Mantis items for discussion

Hi all,
To help with tomorrow's call, here is a condensed list of the un-resolved 
mantis items (currently 44).
This list is generated from Mantis by selecting the filter "Hide Status == 
resolved"

Cheers...
Dave

Id: 830 (http://www.verilog.org/mantis/view.php?id=830)
Summary: Support for breaking out of loops

Id: 2806 (http://www.verilog.org/mantis/view.php?id=2806)
Summary: Direction argument in last_crossing not optional in 4.5.10

Id: 2805 (http://www.verilog.org/mantis/view.php?id=2805)
Summary: Interpolation vs synchronisation of analog values in digital

Id: 2803 (http://www.verilog.org/mantis/view.php?id=2803)
Summary: Why is access to hierarchical port branch syntax disallowed (I(<a1.p>))

Id: 2792 (http://www.verilog.org/mantis/view.php?id=2792)
Summary: $monitor support in Table 9-1 wrong

Id: 2594 (http://www.verilog.org/mantis/view.php?id=2594)
Summary: Ambiguity in list_of_ports syntax item definition.

Id: 2590 (http://www.verilog.org/mantis/view.php?id=2590)
Summary: Semantics of _function_call rules

Id: 2567 (http://www.verilog.org/mantis/view.php?id=2567)
Summary: Syntax/rules for handling escaped quotes

Id: 2459 (http://www.verilog.org/mantis/view.php?id=2459)
Summary: Wrong hyphenation on page 214

Id: 937 (http://www.verilog.org/mantis/view.php?id=937)
Summary: allow discipline attribute change/addition on per net basis

Id: 940 (http://www.verilog.org/mantis/view.php?id=940)
Summary: additional math operator support

Id: 821 (http://www.verilog.org/mantis/view.php?id=821)
Summary: Allowing C-style include syntax for files

Id: 2566 (http://www.verilog.org/mantis/view.php?id=2566)
Summary: VPI related issues in LRM v2.3

Id: 2281 (http://www.verilog.org/mantis/view.php?id=2281)
Summary: disciplines and wreal

Id: 1471 (http://www.verilog.org/mantis/view.php?id=1471)
Summary: cross/above expr_tol default value is not defined in  LRM

Id: 874 (http://www.verilog.org/mantis/view.php?id=874)
Summary: (Ann E) clarifications on usage of vsource

Id: 2378 (http://www.verilog.org/mantis/view.php?id=2378)
Summary: Deprecate wreal

Id: 2162 (http://www.verilog.org/mantis/view.php?id=2162)
Summary: Need ability to assign z to wreal

Id: 866 (http://www.verilog.org/mantis/view.php?id=866)
Summary: Back-Annotation support is non-existant

Id: 2343 (http://www.verilog.org/mantis/view.php?id=2343)
Summary: Connect module instances should be on lower side of ports

Id: 1754 (http://www.verilog.org/mantis/view.php?id=1754)
Summary: Support for auto-connecting implicit ports (e.g. power supplies)

Id: 1854 (http://www.verilog.org/mantis/view.php?id=1854)
Summary: parameter aliases for hierarchical system parameters

Id: 2161 (http://www.verilog.org/mantis/view.php?id=2161)
Summary: register access from analog block

Id: 2160 (http://www.verilog.org/mantis/view.php?id=2160)
Summary: reals and integers should be able to drive event-driven ports

Id: 2159 (http://www.verilog.org/mantis/view.php?id=2159)
Summary: Contributing to a port branch

Id: 828 (http://www.verilog.org/mantis/view.php?id=828)
Summary: Handling of light weight conversions: (a2d, d2a) used through behaviour

Id: 1765 (http://www.verilog.org/mantis/view.php?id=1765)
Summary: Correction of names/insertion point for connect modules

Id: 1638 (http://www.verilog.org/mantis/view.php?id=1638)
Summary: (Ann D) physical constants change

Id: 848 (http://www.verilog.org/mantis/view.php?id=848)
Summary: (Sec 4, Ann A) ddx is currently restricted as analog operator

Id: 831 (http://www.verilog.org/mantis/view.php?id=831)
Summary: (Sec 3?) Ambiguity in indexing of named vector branches as specified 
in LRM

Id: 820 (http://www.verilog.org/mantis/view.php?id=820)
Summary: (Sec 8) Discipline Compatibility issues

Id: 829 (http://www.verilog.org/mantis/view.php?id=829)
Summary: (Sec 12) Issues with VPI

Id: 825 (http://www.verilog.org/mantis/view.php?id=825)
Summary: (Sec 8) Resolving variables to the domain based on assignment context 
is ambigous.

Id: 935 (http://www.verilog.org/mantis/view.php?id=935)
Summary: V(vin[i]) for modeling multiplexers

Id: 904 (http://www.verilog.org/mantis/view.php?id=904)
Summary: No support for absolute delay in the digital context

Id: 936 (http://www.verilog.org/mantis/view.php?id=936)
Summary: enhanced analog/digital event control

Id: 934 (http://www.verilog.org/mantis/view.php?id=934)
Summary: remove restrictions on analog operators

Id: 955 (http://www.verilog.org/mantis/view.php?id=955)
Summary: conditional net discipline coercion

Id: 839 (http://www.verilog.org/mantis/view.php?id=839)
Summary: Default values of idt & ddt nature for derived natures should be 
clarified in LRM

Id: 840 (http://www.verilog.org/mantis/view.php?id=840)
Summary: Support for system task $isPortsShorted

Id: 845 (http://www.verilog.org/mantis/view.php?id=845)
Summary: Restrict usage of type of analog variable that can be used in 'assign' 
statements

Id: 876 (http://www.verilog.org/mantis/view.php?id=876)
Summary: Vector range when they differ in inout and discipline declaration

Id: 814 (http://www.verilog.org/mantis/view.php?id=814)
Summary: Support for global variables using dynamic parameter

Id: 813 (http://www.verilog.org/mantis/view.php?id=813 )
Summary: Support direct import of spice primitives (as defined in Annex E) into 
Verilog-AMS
-- 
==============================================
-- It's a beautiful day
-- Don't let it get away
--
-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
==============================================

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