Minutes of Verilog-AMS technical committee meeting - 9th July

Attendees:

Victor Berman
Karen Pieper
Himyanshu Anand
Kal
Dave Miller
Sri
Martin O'leary
Marq Kole

Accellera v IEEE discussions:
=============================
* Victor Berman, chair for the DASC stds within IEEE, and Karen Pieper 
Accellera technical chair and SV chair participated in the discussions
* There are two proposals at this point
   - raise two PARs for ASVA and SV-AMS work within IEEE and execute it 
as independent projects
   - work with ASVA extensions (and the required Verilog-AMS 
enhancements and P1800 extensions) under Accellera and donate it at that 
point. The SV-AMS integration will also happen in parallel and some of 
the key fundamental issues resolved before donation

* Technically both the above approaches are very feasible. Victor 
mentioned that Accellera will get the approval for copyrights for P1800 
document for this work if the committee decides to stay within Accellera 
for ASVA release. The committee needs to ensure that any enhancements 
done in P1800 is aligned with the overall SV committee and there is a 
plan for these enhancements to be included in their next releases.

* With regards to concern on lengthy process etc, Victor & Karen 
clarified that there is not much of a difference in terms of working 
group execution on regular basis. The process is lengthy only for the 
actual approval process

* For corporate IEEE standards work, Victor clarified that the IEEE 
charges (approx.) 4000 USD. There has been a change in fee structure 
where there is a single fee irrespective of number of projects the 
company is participating (as opposed to the earlier per-project fee 
structure). For individual standards if you are IEEE member there are no 
additional fees for voting rights.

* Martin felt that it might be better to do the ASVA work and the 
related extensions to AMS and SV with Accellera and donate it at that 
point. Given that SV-AMS integration work is happening in parallel, some 
of the key issues for this integration would have been resolved before 
the donation.

* With regards to cleanup and Verilog-AMS enhancements (multi-power 
domain support etc), if it is within Accellera the committee can decide 
whether this gets included as part of the ASVA release or whether an 
earlier release needs to be done.

The next step is to identify feedback from the individuals on the 
participants of the Verilog-AMS and ASVA technical committees. It will 
be good to get a poll of your preference, the options being:
(a) Execute the ASVA work and related Verilog-AMS enhancements within 
Accellera and donate to IEEE at the point of releasing ASVA
or
(b) Donate to IEEE today and raise two PARs to work on these projects

If all of you could let me know your preference by July 28th, it will 
help us make a quick and informed decision.


Analysis of Mantis items:
=========================

* Started looking at the Mantis items. David posted the list of mantis 
items before the meeting. Currently going through the mantis items to 
clean up the database and categorize them appropriately
   - cleanup (minor issue)
   - AMS enhancements (extension to Verilog-AMS language)
   - ASVA extension (requirement to support ASVA work)
   - SV-AMS integration
[Each of the above buckets would be created in Mantis to categorize them 
appropriately]

* The following mantis items were covered in the meeting:
   - 830: Support for breaking out of loops; break, continue and return 
are supported in SV however this cannot be support for "analog-for" 
statements. This will be considered as part of SV-AMS integration
   - 2806: Direction argument in last crossing not optional. This will 
be considered as cleanup item (minor)
   - 2805: Support for both interpolation and synchronization of analog 
values in digital. This will be addressed as part of
   - 2803: Access to hierarchical port branch syntax disallowed 
(I(<a1.p>)). This will be addressed as part of AMS enhancements
   - 2594: Ambiguity in list_of_ports syntax item definition. This is 
already addressed in P1800 and will be addressed as part of SV-AMS 
integration






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