Hi,
Recently I have started to study Verilog AMS to build its analyzer.
I can understand the term "access function" is very important in this
language. In the 2.3.1 LRM, it is mentioned:
3.13.2 Access functions
Each access function name, defined before a module is parsed, is
automatically added to that module’s name space unless there is another
identifier defined with the same name as the access function in that
module’s name space.
I am not clear how another "access function" can be defined inside a
module's name space, as I can understand "access function" can only be
defined by a "nature" or its related "discipline" which can only be
declared outside a module. Can someone please show me an example?
--
Regards
Surya
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Received on Mon Aug 3 01:01:04 2009