Re: Verilog AMS access function namespace

Hello Surya,
This means that if something already exists in the module with the same 
identifier as the access function in the discipline, the access function is 
ignored.
Consider this:

module test;
   analog function real V;
     input i;
     real i;
     begin
       V = i+2;
     end
   endfunction

   electrical a;

   analog begin
     x = V(3.0);  // Calls analog function V()
     x = V(a); // should be error, since V() is UDF.
   end
endmodule

So electrical has a potential access function of V. But we also have the analog 
function V(). This means that in module test, whenever I access V() I ma 
referring to the UDF V().

We don't raise a hard error on this clash as a disciplines file contains many 
disciplines and access functions, most of which never get used.

Hope this helps

Cheers...
Dave


Surya Pratik Saha wrote:
> Hi,
> Recently I have started to study Verilog AMS to build its analyzer.
> 
> I can understand the term "access function" is very important in this 
> language. In the 2.3.1 LRM, it is mentioned:
> *3.13.2 Access functions
> Each access function name, defined before a module is parsed, is 
> automatically added to that module’s name space unless there is another 
> identifier defined with the same name as the access function in that 
> module’s name space.
> *
> I am not clear how another "access function" can be defined inside a 
> module's name space, as I can understand "access function" can only be 
> defined by a "nature" or its related "discipline" which can only be 
> declared outside a module. Can someone please show me an example?
> 
> -- 
> Regards
> Surya
> 
> 
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