RE: UDF description

In digital, Verilog required a function to have at least one argument. All arguments were inputs, so the function was required to have at least one input argument.

In SystemVerilog, a function is not required to have any arguments and arguments can be input, output, inout, or ref.

In any case, if the statement means to say that the block item declaration declares whether the arguments are input, output, or inout, it would be better to call this the "direction" of the argument rather than the "type". "type" is something else.

Shalom
 

> -----Original Message-----
> From: owner-verilog-ams@server.eda.org 
> [mailto:owner-verilog-ams@server.eda.org] On Behalf Of David Miller
> Sent: Tuesday, November 10, 2009 4:29 PM
> To: Paul Floyd
> Cc: Verilog-AMS LRM Committee
> Subject: Re: UDF description
> 
> Hello Paul,
> 
> Yes, sorry. I saw your original email and noted this down as 
> part of the clean 
> up items I am doing. I just forgot to send a response.
> Yes that bullet is confusing - all we really wanted to say 
> was the UDF must 
> have at least one formal argument.
> 
> Your modification is a lot clearer - I will use that as the 
> replacement.
> 
> Regards
> Dave
> 
> 
> Paul Floyd wrote:
> > Hi
> > 
> > I sent this a while back, but never received it from the listserver.
> > 
> > The LRM 2.3.1 has this to say about UDFs.
> > 
> > An analog user defined function:
> > ...
> > - shall have at least one input declared; the block item declaration
> > shall declare the type of the inputs
> > (whether they are input, output, inout)
> > 
> > This doesn't seem to be clear English to me, implying that 
> an UDF can
> > have an "input" that is an "output". Unless I've 
> misunderstood, wouldn't
> > 
> > - shall have at least one formal argument declared; the block item
> > declaration shall declare the type of the formal arguments
> > (whether they are input, output, inout).
> > 
> > be clearer? (Assuming that "formal argument" doesn't need defining).
> > 
> > Regards
> > Paul Floyd
> 
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