RE: Verilog-AMS committee meeting - 18 Nov 2009

Sri,

Can you be in touch with Karen Pieper from P1800? There is a lack of communication between the two committees, and it is not healthy.

Regards,
Shalom 

> -----Original Message-----
> From: Sri Chandra [mailto:sri.chandra@freescale.com] 
> Sent: Wednesday, November 18, 2009 7:48 AM
> To: Bresticker, Shalom
> Cc: Verilog-AMS LRM Committee
> Subject: Re: Verilog-AMS committee meeting - 18 Nov 2009
> 
> 
> Shalom,
> 
> At this current time, I was thinking more along the lines of Option 1 
> that you have mentioned based on P1800-2009. It might be a faster way 
> for the community to have a SV-AMS version, may be I am being 
> optimistic. Also, I felt since this would impact SV in the 
> most minimal 
> fashion might be the easiest approach.
> 
> However, I have not thought into detail on option 3. Just reading 
> through your email, depending on the number of changes in the 2013 
> standard, time frame it will take us to have the 
> merged/extended SV-AMS 
> (depending on resources working on this and other aspects) - we can 
> still look into the option of releasing the extended version based on 
> the 2013 version of SystemVerilog, so that the integrated 
> language has 
> the up to date digital standard. Our initial work can be based on the 
> P1800-2009 standard that is available today.
> 
> Regards,
> Sri
> 
> 
> Bresticker, Shalom wrote:
> > It is necessary to remember that in parallel, P1800 will 
> begin working on a new revision of 1800. 
> > 
> > Is the idea to:
> > 
> > 1. make SV-AMS a set of extensions of SV, similar to how 
> 1800-2005 was a set of extensions of 1364-2005? That would 
> leave 1800 intact and independent, while making SV-AMS 
> dependent on SV.
> > 
> > 2. make SV-AMS an entirely separate standard that would be SV+AMS?
> > 
> > 3. make SV+AMS a single standard, 1800-2013?
> > 
> > 4. undecided yet
> > 
> > Thanks,
> > Shalom
> >  
> > 
> >> -----Original Message-----
> >> From: Sri Chandra [mailto:sri.chandra@freescale.com] 
> >> Sent: Wednesday, November 18, 2009 7:06 AM
> >> To: Bresticker, Shalom
> >> Cc: Verilog-AMS LRM Committee
> >> Subject: Re: Verilog-AMS committee meeting - 18 Nov 2009
> >>
> >>
> >> Dear Shalom,
> >>
> >> I am also bit unclear at this stage on the specifics and 
> >> hence I would 
> >> like to discuss with the committee and hear some of the 
> >> thoughts in this 
> >> regard - what aspects the committee should be focusing on 
> as part of 
> >> this merge process. Any particular ground work in terms of syntax 
> >> differences, semantics, integrated scheduling algorithm 
> >> between the SV 
> >> and AMS engines etc.
> >>
> >> We might have to do something bit different compared to what 
> >> we did with 
> >> 1364-2005 integration. With that integration we pretty much 
> >> merged the 
> >> language at the syntax level first and worked out the 
> >> semantics of each 
> >> of the sections (we merged the entire digital language at 
> the grammar 
> >> level into AMS).
> >>
> >> There are couple of my personal thoughts in this, and I am 
> sure there 
> >> are much better opinions out there. Given that the analog 
> extensions 
> >> will be much smaller compared to the P1800 standard, I 
> >> believe that it 
> >> might be easier to extend the current SV/P1800 standard to 
> >> include the 
> >> AMS extensions. In essence, enhance the current P1800-2009 
> >> standard to 
> >> support analog/mixed signal syntax and semantics and in the 
> >> process see 
> >> whether any of the current SV language constructs are 
> >> applicable to AMS 
> >> and what the common aspects of the two languages are, so 
> that we dont 
> >> define independent semantics for these. But at the more 
> fundamental 
> >> level, there have been some concerns raised in terms of 
> >> integrating the 
> >> scheduling semantics between AMS and SV. I am not yet very 
> >> clear on this 
> >> issue, and why it would be difficult to integrating the scheduling 
> >> engine but we need to understand this more clearly. I am sure 
> >> there are 
> >> many more things to this integration apart from what I 
> have mentioned 
> >> here, but hopefully this will enable other discussions on how 
> >> to address 
> >> this P1800 merge.
> >>
> >> We are currently requesting permissions with Accellera and 
> the P1800 
> >> committee for the original documentation source (framemaker 
> >> documents?)
> >>
> >> Regards,
> >> Sri
> >>
> >>
> >> Bresticker, Shalom wrote:
> >>> Sri,
> >>>
> >>> I am confused about the SV-AMS integration. How is it going 
> >> to work? Who is going to do it? How will it be coordinated 
> >> with P1800? Etc.
> >>> Thanks,
> >>> Shalom 
> >>>
> >>>> -----Original Message-----
> >>>> From: owner-verilog-ams@server.eda.org 
> >>>> [mailto:owner-verilog-ams@server.eda.org] On Behalf Of 
> Sri Chandra
> >>>> Sent: Wednesday, November 18, 2009 6:24 AM
> >>>> To: Verilog-AMS LRM Committee
> >>>> Subject: Verilog-AMS committee meeting - 18 Nov 2009
> >>>>
> >>>>
> >>>> Date: 18 Nov 2009
> >>>>
> >>>> Call-In Details:
> >>>> USA Toll Free      : 8008671147
> >>>> Australia Toll Free: 1800009128
> >>>> India Toll Free    : 0008006501482
> >>>> Netherlands        : 08002658223
> >>>> Passcode: 0970751
> >>>>
> >>>> California: 2.00p (Wednesday)
> >>>> Texas: 4.00p
> >>>> New York: 5.00p
> >>>> Netherlands: 11.00p
> >>>> Israel: Midnight
> >>>> Delhi: 3.30a (Thursday)
> >>>> South Australia: 8.30a
> >>>>
> >>>> Its been more than 4 weeks since the AMS committee met, 
> >> and apologize 
> >>>> for not organizing this meeting earlier. I think it will be 
> >>>> good to have 
> >>>> couple of meetings between now and end of the year to start 
> >>>> discussions 
> >>>> on some of the AMS enhancements tickets and merger activities.
> >>>>
> >>>> Agenda:
> >>>> * Planning for mantis items listed as "AMS Enhancements"
> >>>> * Discussions on how to move forward on SV-AMS integration work 
> >>>> (priorities, initial work break down, discuss the sort of 
> >>>> merger/integration that we plan to do with SV)
> >>>>
> >>>> Regards,
> >>>> Sri
> >>>>
> >>>>
> >>>> -- 
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> >>>>
> >>>>
> >> 
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