Fwd: Agenda for the SystemVerilog Requirements Gathering Meeting

-------- Original Message --------
Subject: Agenda for the SystemVerilog Requirements Gathering Meeting
Date: Thu, 18 Feb 2010 20:47:11 -0800
From: Karen Pieper <karen_l_pieper@yahoo.com>
To: SV-BC eda.org <sv-bc@eda.org>, SV-CC <sv-cc@eda.org>, SV-AC eda.org
<sv-ac@eda.org>, sv-ec <sv-ec@eda.org>, DASC <stds-dasc@eda.org>

Hi, all,

The Agenda for the SystemVerilog Requirements Gathering Meeting can be found at:

http://www.eda.org/twiki/bin/view.cgi/P1800/P1800Agendas

I have uploaded all but one of the presentations (it was too big).

Presenters: Please note the presentation time you have been allotted. There is not any slack in the schedule, so we need to run the meeting on schedule. Be prepared to limit yourself to the time given.

See you there!

Karen

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