RE: call for participation in SV-DC (PWL)

Transient analog simulators generally work by stepping discretely
through time, at each time-point the circuit model is evaluated and the
next time-point calculated. So signals are stored as a current value
and a next value (or equivalently: value and derivative). In a
mixed-signal simulator the digital simulation continues stepping from
the current time to the next analog time-point using interpolation to
calculate the analog values.

What I'd like to do is take that functionality (currently buried in the
simulator) and bring it up to the language level.

The "joints" are just discrete changes in the derivative, if you view
the signal as a composite type where the derivative is just a value, you
can handle it the same as any other composite type data change, i.e.
there is little difference between handling a user defined type with
multiple fields and a PWL signal. The question is how to abstract the
interpolation and crossing functions into (say) the ADMS_signals
classes, at which point the representation of the values (e.g. real,
complex) becomes immaterial.

Kev.

On 05/18/2010 07:07 AM, John Havlicek wrote:
> Hi Kevin:
>
> I guess that you mean that the sequence of points is monotonic and has
> no limit point in the space of real numbers? And that the value and
> derivative for each such point are specified by real numbers?
>
> That would be close to my intuition for piecewise linear, although it is
> "left" biased. My intuition does not dictate the function's behavior at
> the "joints". Are you imagining continuous piecewise linear functions?
>
> J.H.
>
> -----Original Message-----
> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
> Behalf Of Kevin Cameron
> Sent: Tuesday, May 18, 2010 3:13 AM
> To: Bakalar, Kenneth
> Cc: verilog-ams@eda.org
> Subject: Re: call for participation in SV-DC (PWL)
>
>
> PWL support just means allowing waveforms defined as a sequence points
> or values and derivatives - it's the derivative that changes discretely.
> The boundary between analog/digital is easier to handle using PWL
> waveforms, and they can be used to describe analog behavior better than
> (say) discrete real values.
>
> Cross-type driver resolution gives you the ability to mix different
> (user defined) drivers on a net, e.g. rather than using full analog
> models, how can you use models with real-valued/PWL signals in a similar
> way (maybe just a generalization of the connect module approach).
>
> Kev.
>
> On 05/17/2010 09:27 AM, Bakalar, Kenneth wrote:
>
>> Hi Scott,
>>
>> Could you elaborate on what you mean by PWL support and cross-type
>> driver resolution? I want to take up the challenge of building these
>> on top of the ADMS_signals package. It may be that it not too ugly.
>>
>> Best Regards,
>> Ken
>>
>> -----Original Message-----
>>
>
>> ...
>>
>
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