Re: call for participation in SV-DC (PWL)

But to support discrete time only simulation, I would encourage this to be defined as current value + rate.
This would allow a model to calculate the time of future events.
 btw I have not been seeing a need for this in any design I've worked on for the last three years. Simple discrete time real signals are sufficient in most cases.
I did hear some discussion about back annotation. Primarily I see this as a need for timing closure for logic. And I don't see these real wires as part of this - the current digital timing annotation is generally sufficient. And any back annotation extensions should be compatible with that type of flow.
Jonathan

Sent from my iPod

On May 18, 2010, at 1:13 AM, Kevin Cameron <edaorg@v-ms.com> wrote:

PWL support just means allowing waveforms defined as a sequence points
or values and derivatives - it's the derivative that changes discretely.
The boundary between analog/digital is easier to handle using PWL
waveforms, and they can be used to describe analog behavior better than
(say) discrete real values.

Cross-type driver resolution gives you the ability to mix different
(user defined) drivers on a net, e.g. rather than using full analog
models, how can you use models with real-valued/PWL signals in a similar
way (maybe just a generalization of the connect module approach).

Kev.

On 05/17/2010 09:27 AM, Bakalar, Kenneth wrote:
Hi Scott,

Could you elaborate on what you mean by PWL support and cross-type
driver resolution? I want to take up the challenge of building these on
top of the ADMS_signals package. It may be that it not too ugly.

Best Regards,
Ken

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