ADMS_Signals: Nets of User-defined Type in Standard SystemVerilog for Event-driven Analog Modeling

Ken,

You had sent across a proposal as part of the wreal discussion/donation.
I had scheduled it last week as part of the AMS committee meeting
agenda, but you didn't join the call.

Unfortunately, I forgot to send a meeting reminder for the wednesday
(5/26) AMS committee meeting.

So, I would like to ask whether you would be able to present this
proposal at the next committee meeting on the 2nd of June. If so, I will
include it as part of the agenda. Please confirm.

Regards,
Sri

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