Port directions

From: David Miller <David.L.Miller@freescale.com>
Date: Wed Jun 02 2010 - 12:00:30 PDT

Should the language enforce that port directions are honored?
Specifically ports that are defined as input, should it be a error if you
contribute to a branch containing that port?

module mymod(a,b);
   electrical a,b;
   input a,b;
   analog V(a,b) <+ 5;
endmodule

Should this be an error, since a,b are input?

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Received on Wed Jun 2 12:00:47 2010

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