Re: Port directions

Best to view it as an "advisory" attribute for digital use, it's pretty
difficult to come up with a sensible meaning for it in a
mixed-signal/analog context. If I remember correctly from the guys at
Nat Semi found some tools just ignore it, others interpreted it to mean
something and netlists were incompatible.

In particular: if you drop in a passive component (say parasitic
capacitance) you don't really want to consider that a violation of the
"input" status, but it's pretty hard to tell that's what's going on from
the syntax.

Kev.

On 06/02/2010 12:24 PM, Ken Kundert wrote:
> No. The direction is mainly used to determine which connect modules to
> use when connecting to the port. The ability to contribute to inputs is
> needed so as to be able to model input loading (input resistance, input
> capacitance, etc.)
>
> -Ken
>
> On 06/02/2010 12:00 PM, David Miller wrote:
>
>> Should the language enforce that port directions are honored?
>> Specifically ports that are defined as input, should it be a error if
>> you contribute to a branch containing that port?
>>
>> module mymod(a,b);
>> electrical a,b;
>> input a,b;
>> analog V(a,b) <+ 5;
>> endmodule
>>
>> Should this be an error, since a,b are input?
>>
>>
>>
>

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