RE: Port directions

Hi Kevin, Ken,

I can understand not wanting to impose this limitation for conservative disciplines, but how about signal-flow disciplines? There you want to make sure that not more than one driver exists for a potential-only discipline or more than one sink for a flow-only discipline.

Cheers,
Marq

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of David Miller
Sent: Wednesday 2 June 2010 21:01
To: Verilog-AMS LRM Committee
Subject: Port directions

Should the language enforce that port directions are honored?
Specifically ports that are defined as input, should it be a error if you
contribute to a branch containing that port?

module mymod(a,b);
   electrical a,b;
   input a,b;
   analog V(a,b) <+ 5;
endmodule

Should this be an error, since a,b are input?

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