Re: Port directions

How are you going to recognize signal flow?

You might want to try addressing this issue in the assertions committee
- i.e. if you can make up some rule about
drivers/contributions/disciplines that can be tested then this problem
moves into user space (being programmable) rather than being
hard-defined in the standard.

Kev.

On 06/03/2010 02:26 AM, Marq Kole wrote:
> Hi Kevin, Ken,
>
> I can understand not wanting to impose this limitation for conservative disciplines, but how about signal-flow disciplines? There you want to make sure that not more than one driver exists for a potential-only discipline or more than one sink for a flow-only discipline.
>
> Cheers,
> Marq
>
> -----Original Message-----
> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of David Miller
> Sent: Wednesday 2 June 2010 21:01
> To: Verilog-AMS LRM Committee
> Subject: Port directions
>
> Should the language enforce that port directions are honored?
> Specifically ports that are defined as input, should it be a error if you
> contribute to a branch containing that port?
>
> module mymod(a,b);
> electrical a,b;
> input a,b;
> analog V(a,b) <+ 5;
> endmodule
>
> Should this be an error, since a,b are input?
>
>
>

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.