Verilog-AMS Committee Meeting Minutes - 9 June 2010

Date: 9 June 2010

Dave C, Synopsys
Ian W, Berkeley DA
Shalom B, Intel
Sri C, Freescale
Ken B, Mentor
David.M, Freescale
Martin.L, Cadence
Scott L, Freescale

Minutes:
   * Ken went through his proposal "ADMS_Signals: Nets of User-defined
Type in Standard SystemVerilog for Event-driven Analog Modeling"
   * This proposal could be found in Verilog-AMS website:
http://www.eda.org/verilog-ams/htmlpages/public-docs/ResolvedCompositeSignalsInSVv4.pdf
   * Ken mentioned that there is a SV-DC committee also working on some
of the extensions to solve discrete modeling issues. This committee is
looking at some of the additional enhancements in this aspect
   * Martin raised a concern that AMS activities may not be tied into
the work done by SV-DC and hence cause for concern/misalingment when we
come to merge. Need to understand SV-DC enhancements (Scott has sent
followup email on the activities of this committee)
   * Ken mentioned that the current proposal and the examples quoted are
using SV language as it exists today (no extensions).
   * Brief discussion of "disciplines" concept in SV language (with SV-AMS?)
   * Details of the proposal can be read in the above web link.

Regards,
Sri

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