Fwd: Re-starting focus on SV-AMS integration efforts

FYI. Reminder for call tomorrow.

Regards,
Sri

-------- Original Message --------
Subject: Re-starting focus on SV-AMS integration efforts
Date: Tue, 13 Jul 2010 23:26:58 +0530
From: Chandrasekaran Srikanth-A12788 <A12788@freescale.com>
Organization: Freescale Semiconductor, Inc.
To: Verilog-AMS LRM Committee <verilog-ams@eda.org>

Hi all,

Its been a while since since I have scheduled a call to have discussions
and focus on the SV-AMS integration efforts. This was mainly because
(apart from being little bit side-tracked with other activities the last
few weeks) I was trying to figure out what is the best way the committee
can move forward in effectively (and efficiently) integrating the
P1800-2009 standards (and the latest enhancements with P1800) with the
Verilog-AMS LRM 2.3.1 version.

I would like to have a brainstorm on this activity as part of the
committee meeting on 21st July and share my current thoughts for the
integration efforts and discuss how we plan this work (and the resources
that are available to work on the integration). I have had few
conversation with some of the people in the committee and I will share
those ideas as part of the brainstorm and would like to hear further
ideas from the committee. Graham has also done some initial activity in
working on a comparison grammar between SV and Verilog-AMS, which we
have reviewed in earlier calls, which is a very good starting point for
these discussions. I believe Graham's documents are already posted on
the reflector.

I will send in another reminder before the meeting next week.

The call in details (and times) are as follows:

Date: 21st July 2010

California: 6.00a (Wednesday)
Texas: 8.00a
New York: 9.00a
Netherlands: 3.00p
Israel: 4.00p
Delhi: 6.30p
South Australia: 10.30p

Call-In Details:
USA Toll Free : 8008671147
Australia Toll Free: 1800009128
India Toll Free : 0008006501482
Netherlands : 08002658223
Passcode: 0970751#

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