Verilog-AMS committee meeting minutes - 21 July 2010

From: Sri Chandra <sri.chandra@freescale.com>
Date: Tue Jul 27 2010 - 21:22:34 PDT

Attendees:

Shalom Bresticker, Intel
Graham Helwig, ASTC
Walter, Cadence
Dave Miller, Freescale,
Top Lertpanyavit, Intel
Sri Chandra, Freescale

Minutes:

* Main agenda item was on SV P1800-2009 and Verilog-AMS integration
   - Graham had done some initial work few months back in the comparison
of grammars and documented the differences between the languages.
   - Discussion on starting with looking at the BNF of the two languages
and put an initial first pass integrated BNF
   - Everybody was in agreement that the first pass of an integrated
grammar will target a minimal interface/interaction between P1800 and
AMS to enable mixed signal simulation with SV and AMS modules.
   - Graham agreed that he will start working on a draft BNF continuing
from his earlier work with help from Dave Miller from Freescale with
this BNF integration work. He will also look at the keywords document,
probably start from here.
   - For, P1800-AMS the AMS extensions would be included as part of the
P1800 document, with integrated BNF and annexes to document analog
extensions support (as opposed to the work done in Verilog-AMS LRM2.3
where digital was integrated into existing AMS document)
   - There was a question on what work is already existing in this area?
This was unclear as there was not enough tool development
representatives but initial feedback was minimal.
   - Need to look at some of the feature support that would be required
in the integrated SV-AMS. Need to carefully look at what SV features
need to be imported in AMS. Graham will look at this aspect as part of
language development.
   - Timeframe: Very early to judge. Sri's comments/initial thoughts:
Prior experience with AMS/P1364 merger took about 3+ years. The next
release coming out of Accellera would be focused on assertions
extensions (and they have requirements on Verilog-AMS and SV) - possibly
mid-late 2011? At that point the committee will look at donation of
Verilog-AMS and continuing with the rest of integration work with IEEE.
By that stage we will have a fairly good understanding of the
integration and the donation. Possibly late 2012 for a release?
   - Shalom commented that earlier work was done based on P1800 draft
version. Need to ensure we are using released version as there was some
changes done as part of review feedback.

Next call: Meet once-in-2-weeks. 4th August. We can review if there are
initial BNF documents posted.

Regards,
Sri

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