Re: Agenda - Verilog-AMS committee meeting 25th August 2010

On 08/24/2010 07:52 AM, David Miller wrote:
> ....
> Some of the questions that will be raised with the next review are:
>
> Q1: Can existing systemVerilog real net type be used instead of the
> AMS wreal construct?
>
> Q2: Can wreal and ground included as part of the net_type
> SystemVerilog syntax item?
>
> Q3: The reg_declaration syntax item is not defined in SystemVerilog
> syntax. By adding the optional discipline_identifier into the
> net_declaration SystemVerilog syntax item, does the a reg keyword
> declaration use the optional discipline_identifier syntax?

The SV-DC committee is looking at how user-defined types should work in
SV for discrete modeling of analog things, which includes real/wreal.
Seems redundant to be doing it in the AMS committee. The meaning of
"reg" has been under debate too.

To put it another way: SV is a moving target, assuming any of it will be
the same at the next release is not a good idea.

Kev.

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