Re: Agenda - Verilog-AMS committee meeting 25th August 2010

Short call, not enough attendees.

Only two actions - I will send Graham a list of the SV keywords (p1800-2009). I
will also update Mantis to track the issues raised with the previous call.

Next call scheduled for 2 weeks - 8th Sept 2010, same agenda as below.

Cheers...
Dave

On 08/24/2010 09:52 AM, David Miller wrote:
> California: 6.00a (Wednesday)
> Texas: 8.00a
> New York: 9.00a
> Netherlands: 3.00p
> Israel: 4.00p
> Delhi: 6.30p
> South Australia: 10.30p
>
> Call-In Details:
> USA Toll Free : 8008671147
> Australia Toll Free: 1800009128
> India Toll Free : 0008006501482
> Netherlands : 08002658223
> Passcode: 0970751#
>
> We will be continuing the review of the initial grammar, picking up at Type
> Declarations (pg 13/60).
>
> The document can be found at:
> http://www.eda-stds.org/verilog-ams/htmlpages/public-docs/SystemVerilogMerge/annexA_bnf_merged_v2.pdf
>
>
> After first review, I think our focus should not be so much on the
> correctness/formatting etc. of the document as it will go through many
> revisions, but more on whether the merge points between the Verilog-AMS and
> System Verilog languages that have been identified make the most sense.
>
> Some of the questions that will be raised with the next review are:
>
> Q1: Can existing systemVerilog real net type be used instead of the AMS wreal
> construct?
>
> Q2: Can wreal and ground included as part of the net_type SystemVerilog syntax
> item?
>
> Q3: The reg_declaration syntax item is not defined in SystemVerilog syntax. By
> adding the optional discipline_identifier into the net_declaration
> SystemVerilog syntax item, does the a reg keyword declaration use the optional
> discipline_identifier syntax?

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-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
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