Re: Verilog-AMS Work Moving Forward

Is it a good idea to merge the SVA work into Verilog-AMS prior to the SystemVerilog merger? Currently there is no apparent buy-in from from the SystemVerilog committee for it (or the rest of AMS), and I suspect they'll want to rework it if it gets there.

This seems to be falling into the same pattern as before where there is work on a "combined BNF" and then a new Verilog-AMS LRM get released instead of the merger.

I would prefer to see a commitment to no new Verilog-AMS LRMs until the SV integration is properly underway.

Kev.

On 11/10/2010 02:54 PM, David Miller wrote:
> Hello all,
>
> Next call is scheduled for next week - Thursday 18th Nov. Call in details below.
>
> We have now finished the initial review of the merged SV-AMS grammar - I will post that to the website later tonight.
>
> Where too from here?
>
> We have two main focuses.
>
> First is the SVA work. The intention is that we will merge the assertions work into the existing Verilog-AMS LRM and release a version 2.4 most likely 2nd half next year.
>
> The SVA workgroup will supply the necessary changes that they would like to include into the AMS LRM. This will not be a full integration of the SVA feature set into AMS. Just the required subset needed in the language as it stands today.
>
> The question we need to address is, for this version, do we fix some of the minor requests (VAMS_Cleanup items in Mantis) in this 2.4 version as well or should be hold off on doing that and only address what is needed for the assertions merge. There are currently ~14 items that have been categorized as VAMS_Cleanup.
>
>
> The second and main focus is the SV merge itself. The first decision is the layout of the document itself. The SV document is divided up into 4 main sections:
> Part One: Design and Verification Constructs
> Part Two: Hierarchy Constructs
> Part Three: Application Programming Interface
> Part Four: Annexes
>
> Do we want to replicate this layout to be consistent with the P1800-20XX document?
>
> If we do this, will it be ok to have chapters where we have nothing to add. For example, "28. Gate-level and switch-level modeling" might simply contain a "Refer to P1800-20XX ..." sentence, since we would have nothing to add to this.
>
> I will post a layout (ToC) of the SV document later tonight for those that don't have access to the P1800-2009.
>
> Next is the actual section changes. Now is the time for some volunteers to take ownership of one or more chapters. Not necessarily to do the actual changes at this stage, just a first pass to identify the required changes for each chapter.
> With the year coming to a close, it would be nice to assign some sections now, so that people have a couple months to go through it and report back early next year.
> So if there is a particular part of the document you would like to work on, let me know, and we can start coordinating our efforts.
>
> We will meet next week Thursday 18th Nov to discuss this all in more detail. I will send a reminder next Tuesday.
>
> Call times have now changed to:
> San Francisco, 11.30a
> Austin, 1.30p
> Boston, 2.30p
> Amsterdam, 8.30p
> Tel Aviv, 9.30p
> New Delhi, 1a (next day)
> Adelaide, 6a
>
> Call-In Details:
> USA Toll Free : 8008671147
> Australia Toll Free: 1800009128
> India Toll Free : 0008006501482
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> Passcode: 0970751#
>
> Cheers...
> Dave
>
>

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