Verilog-AMS committee meeting - 18 Oct 2010

Agenda:
  * Update on the SV-DC working group progress. This is related to the SV
Assertions work we would like to merge into Verilog-AMS.
  * Discuss details of work required now that we have an initial version of the
merged syntax. Refer to email:

   Date: Wed, 10 Nov 2010 16:54:32 -0600
   From: David Miller <David.L.Miller@freescale.com>
   To: Verilog-AMS LRM Committee <verilog-ams@eda.org>
   Subject: Verilog-AMS Work Moving Forward

Latest version of merged grammar and outline of the P1800-2009 ToC can be found at:

http://www.eda-stds.org/verilog-ams/htmlpages/cdd.html

Please note the change in call times:
San Francisco, 11.30a
Austin, 1.30p
Boston, 2.30p
Amsterdam, 8.30p
Tel Aviv, 9.30p
New Delhi, 1a (next day)
Adelaide, 6a

Call-In Details:
USA Toll Free : 8008671147
Australia Toll Free: 1800009128
India Toll Free : 0008006501482
Netherlands : 08002658223
Passcode: 0970751#

Cheers...
Dave

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