RE: Verilog-AMS Committee Meeting Minutes - 17th Feb 2011

Hi Dave,
Some clarification on the 1076.1 LRM since I am intimately involved with it.

The 1076.1 LRM takes the version of the 1076 document on which it is based and adds/modifies the document to include all of the AMS extensions. This has been pretty straightforward to manage until the 2008 version of 1076 when the VHDL LRM was restructured. Even there it is not going to be a major headache.
The fundamental requirement for 1076.1 is that it is a superset of 1076 so that the entire 1076 language is part of 1076.1 and not just by reference. It allows for a more holistic view of the language by the user community and forces us to make sure that any changes we make in 1076.1 are compatible with 1076. It also makes it easy for the 1076 committee to understand the additions due to 1076.1.

So, while I know it appears easier to create a separate document from P1800 for SystemVerilog I think that is a mirage. All of the effort of keeping the semantics and BNF in sync have to go on anyway and the extensions can be made in such a way that the disruption to the original P1800 document is small. The advantage is that you have to really understand the entire P1800 language and acknowledge your dependencies. That is a true regardless of the form of the document but keeping them documented the same facilitates it.

My 2 cents worth at least.

Regards
David

David W. Smith
Synopsys Scientist
 
Synopsys, Inc.
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124

Voice: 503.547.6467
Main:  503.547.6000
Cell:    503.560.5389
FAX:   503.547.6906
Email: david.smith@synopsys.com
http://www.synopsys.com
 
Saber Accelerates Robust Design
Predictable. Repeatable. Reliable. Proven.

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Dave Miller
Sent: Friday, February 18, 2011 9:30 AM
To: Verilog-AMS LRM Committee
Subject: Verilog-AMS Committee Meeting Minutes - 17th Feb 2011

Meeting - Thursday 17th February 2011

Attendees:
Sri Chandra (Freescale)
Geoffrey Coram (Analog Devices)
Scott Little (Freescale)
David Miller (Freescale)

* Update from recent SV committee meeting Sri recently participated in the System Verilog committee meeting and discussed what we plan to do with respect to the System Verilog-AMS merge.
Main discussion was with respect to the document.
Discussed both option:
1. get all chapters and incorportate analog entensions to produce one fully contained System-Verilog-AMS document.
2. Just obtain the style sheets and generate an extensions document. This would be similar to what we have now with the Verilog-AMS 2.3.1 and 1364-2005.

The SV board was a lot more comfortable with 2.

It also means we don't have to do a complete review of our document every time the parent P1800 document changes especially since our time lines may not sync up.

The next item that was discussed was the BNF, do we want to have an appendix that is just the AMS changes to the P1800 or do we want to support a single merged BNF? Still undecided, but feel the most useful option is a single merged BNF. Yes, it does mean we need to keep it up to date with changes in the parent
P1800 BNF, but changes in the BNF are not quite as drastic as the potential document changes between revisions.

Lynn Horobin is working with Accellera and P1800 to get the necessary permissions in place to access the documents.

We made need some sort of restrictive access, or access list put in place, this is still being looked into.

There was some discussion on how VHDL 1076 works, with the 1076.1 dot standard for the AMS extensions being a similar work effort to what we are undertaking.
It is referred to as a superset of 1076 and does mention that it may not be in sync with the parent 1076 standard.

* Other items
Achim sent some requests for enhancements to the Verilog-AMS standard. They have been lodged as Mantis item: 3392.

Dave asked a question related to the request by Jonathan regarding detecting of floating node conditions during run time.

Geoffrey explained that they are not ideal floating nodes, but situations where for example, a MOS device is turned off. The node may exhibit a very tiny conductance and be very loosely controlled. It is these high impedance nodes that people are interested in detecting. If the tools could detect these conditions, it would be very useful.

The next call will be Thursday 3rd March.

An agenda will be distributed two days prior to the call.

Dialin Details:
San Francisco, 11.30a
Austin, 1.30p
Boston, 2.30p
Amsterdam, 8.30p
Tel Aviv, 9.30p
New Delhi, 1a (next day)
Adelaide, 6a

Call-In Details:
USA Toll Free : 8008671147
Australia Toll Free: 1800009128
India Toll Free : 0008006501482
Netherlands : 08002658223
Passcode: 0970751#

--
==============================================
-- It's a beautiful day
-- Don't let it get away
--
-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
==============================================
-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.
-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.