Re: Verilog-AMS Committee Call - 14th Apr 2011 (primitives?)

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Something that came up in discussions -

The proposal mentions the use of primitives, but gives no indication how components like pmos, nmos etc. will work with user-defined types. http://www.asic-world.com/verilog/vqref1.html#GATE_PRIMITIVES

I would suggest looking back at the 3-D nettype proposals/suggestions on the sv-dc reflector, which I think provides a mechanism which will make it "just work" without a lot of extra syntax/semantics.

Kev.

On 04/13/2011 06:30 AM, Dave Miller wrote:
> Hello all,
> we have a call scheduled for Thursday 14th April 2011.
>
> Agenda:
>
> We will be reviewing the user defined net type proposal from the SV-DC committee.
> The proposal can be found at:
> http://www.eda.org/twiki/pub/VerilogAMS/AmsDiscussionDoc/UserNettypes_v3.pdf
>
> To ensure that the call remains within the scheduled 1hr time frame we wish to limit the discussion to potential negative impacts the proposal may have on the Verilog-AMS / SV merge only.
> We do not want to discuss if there is an alternative way for the SV-DC group to implement real valued modeling within SV. We just want to make sure that the proposal as it stands today, doesn't restrict our work.
>
> Please note the new times (Thursday 01.00pm UTC):
>
> San Francisco, Thurs 06.00a
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> New Delhi, 06:30p
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>
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>
> Regards
> Dave
>

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