Verilog-AMS Committee Meeting Minutes - 14th Mar 2011

Meeting - Thursday 14th March 2011

Attendees:
============
Gordon Vreugdenhil (Mentor)
Achim Bauer (EXL Modeling)
Marq Kole (NXP)
Ian Wilson (BDA)
Shalom Bresticker (Intel)
Ken Bakalar (Mentor)
Scott Little (Freescale)
Abhijeet Kolpekwar (Cadence)
Martin O'Leary (Cadence)
Dave Miller (Freescale)

* User Defined Nettype
Gordon presented the SV-DC proposal for defining user defined nets within SV
http://www.eda.org/twiki/pub/VerilogAMS/AmsDiscussionDoc/UserNettypes_v3.pdf

The SV-DC committee is looking at the implementation of real values modeling
within SystemVerilog.
The SV-DC group is not part of Verilog-AMS/Accellera. They are a working group
within P1800.
They are not implementing or merging sections of Verilog-AMS into SV. However
since the real valued modeling is also part of the Verilog-AMS standard (wreal)
we agreed that it would be a good idea for the Verilog-AMs committee to look
over the proposal to make sure that it doesn't introduce any potential
conflicts (keywords, contructs, etc.) that might impact the Verilog-AMS/SV merge.

During the development of the proposal, the SV-DC group have kept in mind the
wreal construct used within Verilog-AMS to ensure that what they propose will
be able to support existing wreal functionality.

Gordan noted that the interaction of user defined nets with the primitives,
especially the switchtype (nmos, pmos) still needs to be resolved.
Ken pointed out that this will be one area that may have an impact on AMS.

The Verilog-AMS group is encourage to review the proposal over the next week or
so to see if there are any conflicts which might cause us problems. We can then
feed those back into the SV-DC group.

The SV-DC group is expecting to be able to vote on this proposal by the end of
next month. This proposal is currently on track to be included in the current
P1800 par.

Next call scheduled for Thurs 28th Apr.

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-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
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