Re: Verilog-AMS Committee Call - 16th June 2011 (SV-DC)

There really isn't a good reason not to consider all interconnect as generic and collapsed by default. Verilog (and SV) only really has one wire type (strength logic), and it doesn't matter whether you resolve it hierarchically or flat, so you might as well just assume it's flat, and all physical wire types going forward are resolved flat since thats the only thing that works generally. As such the extra keyword (interconnect) is redundant, and nobody wants to have to go back and rewrite structural Verilog to put it in anyway.

Nobody so far has indicated to me where any existing Verilog breaks if you just consider all connections as being generic and collapsed.

I would suggest asking for a complete proposal that meets all the requirements (in mantiss) before discussing the detail. I.e. Gord should resolve the open issues with his proposal before continuing with it.

For comparison my own proposal meets all the requirements -

    http://www.eda.org/twiki/pub/VerilogAMS/DiscreteAnalogModelingInSV/3398-alt.pdf

- let me know if you think it doesn't. Ken's proposal is also on the website -

   http://www.eda.org/twiki/pub/VerilogAMS/AmsDiscussionDoc/ResolvedCompositeSignalsInSVv4.pdf

Kev.

On 06/14/2011 12:09 PM, Dave Miller wrote:
> The next call is scheduled for Thursday 16th June.
>
> Agenda
>
> * Update on SV-AMS document merge direction and outstanding action items.
> * Discussion regarding the Generic Interconnect proposal by SV-DC. I have tried to collect all the relevant proposal and correspondence into a single page: http://www.eda.org/twiki/bin/view.cgi/VerilogAMS/GenericInterconnect
>
> If possible please give this some thought prior to the meeting. If we could come up with 4-5 points of what we would require in a generic interconnect for mixed signal, it would make it a lot easier for us to ensure the the SV-DC proposal covers our requirements.
>
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