Re: Verilog-AMS Committee Call - 16th June 2011 (SV-DC)

There was a long discussion about generic interconnect in today's (6/15)
SV-DC
meeting.

Of particular value today, I found one user's complaint (paraphrased):
   - vendor X implemented [a form of] wreal and allowed interconnection
     [of wreal ports] using wire
   - vendor Y's wreal implementation did not support interconnection using
     wire
In other words, there was no portability between these two implementations
(and no standard exists for a 'correct' interpretation).

The only candidate in existing {System}Verilog for a typeless
interconnect is wire.
However, this is predfined as being of type logic, so would be
incompatible on some
level with user-defined types (which would be the mechanism for
providing portable
behavior similar to wreal). Hence the proposal to introduce
'interconnect' as a type.

 From an AMS viewpoint, interconnect (whether wire or something) doesn't
have
any behavior except possibly to contribute discipline information, so
other than
complicating the elaboration process, and adding syntax, it doesn't seem
that
interconnect as currently proposed will be a major problem for AMS/SV
integration.

--ian
> ----------------------------------
> Ian M Wilson
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