RE: Verilog-AMS Committee Call - 16th June 2011 (SV-DC)

Regd:

> Of particular value today, I found one user's complaint (paraphrased):
> - vendor X implemented [a form of] wreal and allowed interconnection
> [of wreal ports] using wire
> - vendor Y's wreal implementation did not support interconnection using
> wire
> In other words, there was no portability between these two implementations (and no standard exists for a 'correct' interpretation).

According to Verilog-AMS LRM v2.3.1 at:
http://www.eda.org/verilog-ams/htmlpages/public-docs/lrm/2.3.1/VAMS-LRM-2-3-1.pdf

In Page 44, section 3.5, here is a line from the 2nd paragraph:

"When the two nets connected by a port are of net type wreal and wire/tri, the resulting single net will be assigned as wreal."
 
Based on this, we can see that vendor X complies with the LRM while vendor Y doesn't. Besides, there is also a standard which defines how those connections should be interpreted.
cheers,
Shekar.

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Ian Wilson
Sent: Wednesday, June 15, 2011 11:34 AM
To: Verilog-AMS LRM Committee
Subject: Re: Verilog-AMS Committee Call - 16th June 2011 (SV-DC)

There was a long discussion about generic interconnect in today's (6/15) SV-DC meeting.

Of particular value today, I found one user's complaint (paraphrased):
   - vendor X implemented [a form of] wreal and allowed interconnection
     [of wreal ports] using wire
   - vendor Y's wreal implementation did not support interconnection using
     wire
In other words, there was no portability between these two implementations (and no standard exists for a 'correct' interpretation).

The only candidate in existing {System}Verilog for a typeless interconnect is wire.
However, this is predfined as being of type logic, so would be incompatible on some level with user-defined types (which would be the mechanism for providing portable behavior similar to wreal). Hence the proposal to introduce 'interconnect' as a type.

 From an AMS viewpoint, interconnect (whether wire or something) doesn't have any behavior except possibly to contribute discipline information, so other than complicating the elaboration process, and adding syntax, it doesn't seem that interconnect as currently proposed will be a major problem for AMS/SV integration.

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