Verilog-AMS committee meeting minutes - 16 June 2011

[Apologies for the delay in sending the minutes]

Date: 16 June 2011

Attendees:
Ken Bakalar, Mentor
Ian Wilson, Berkeley DA
Dave Miller, FSL
Scott Little, FSL
Geoffrey Coram, Analog Devices
Dave Cronauer, Synopsys
Sri Chandra, FSL

Update on document editing

    * Working with P1800 committee to get the original frame source of
      2009 version. Document edits will be done to keep on the P1800 version
    * For the time being, a word document is being generated which
      records the changes and updates required in the final merge, until
      Accellera committee gets access to the source.
    * We need further contribution/volunteers to participate in this
      effort to make this successful and in a meaningful timeframe.
      Currently there is not enough contribution on the various chapters
      apart from Dave Miller and Graham Helwig.

Interconnect proposal from SV-DC committee

    * Discussion on SV-DC proposal on user defined net types and using
      generic interconnect objects
    * The proposal from SV-DC as it stands today seems to be fine from
      the Verilog-AMS technical committee. Currently this is done in AMS
      through the overloading of the "wire" concept, which is not
      probably the right way to go about. The new proposal does not seem
      to break backward compatibility.
    * Discussions around wreal and its connection mechanism to wire?
    * How does the current usage of discipline work with the user
      defined net types?
          o The aspect of disciplines is outside the scope of this work
            from SV-DC and there is no intention to look at that.
          o How will this be handled in SV-AMS integration? The AMS
            technical committee also feels it is not good idea to
            overload "electrical discipline" and prefers the usage of
            "interconnect" keyword that is specified in the proposal
          o There seems to be lack of clarity, based on discussions, on
            the intent of the discipline used in Verilog-AMS vs net type.
    * The interconnect proposal is purely to specify structural
      connections to bridge the gap in SV where there was no structural
      connection available in SV before
    * The current connectivity syntax in SV is very restrictive - only
      real to real connection; done on intent
          o Possibly look at removing the restrictions as we move
            forward with SV-AMS

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